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| L6388 HIGH-VOLTAGE HIGH AND LOW SIDE DRIVER 1 FEATURES HIGH VOLTAGE RAIL UP TO 600 V dV/dt IMMUNITY 50 V/nsec IN FULL TEMPERATURE RANGE DRIVER CURRENT CAPABILITY:400 mA SOURCE,650 mA SINK SWITCHING TIMES 70/40 nsec RISE/FALL WITH 1nF LOAD 3.3V, 5V, 15V CMOS/TTL INPUTS COMPARATORS WITH HYSTERESYS AND PULL DOWN INTERNAL BOOTSTRAP DIODE OUTPUTS IN PHASE WITH INPUTS DEAD TIME AND INTERLOCKING FUNCTION Figure 1. Package SO8 DIP8 Table 1. Order Codes Part Number L6388 L6388D L6388D013TR Package DIP8 SO8 SO8 in Tape & Reel It has a Driver structure that enables to drive independent referenced N Channel Power MOS or IGBT. The Upper (Floating) Section is enabled to work with voltage Rail up to 600V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices. 2 DESCRIPTION The L6388 is an high-voltage device, manufactured with the BCD"OFF-LINE" technology. Figure 2. Block Diagram BOOTSTRAP DRIVER 8 Vboot H.V. Cboot VCC 3 UV DETECTION LOGIC UV DETECTION R R HVG DRIVER 7 HVG HIN 2 SHOOT THROUGH PREVENTION 1 LEVEL SHIFTER S VCC OUT 6 5 LVG DRIVER LVG TO LOAD LIN 4 GND May 2005 Rev. 2 1/11 L6388 Table 2. Absolute Maximum Rating Symbol Vout Vcc Vboot Vhvg Vlvg Vi dVout/dt Ptot Tj Tstg Output Voltage Supply Voltage Floating Supply Voltage High Side Gate Output Voltage Low Side Gate Output Voltage Logic Input Voltage Allowed Output Slew Rate Total Power Dissipation (Tj = 85C) Junction Temperature Storage Temperature Parameter Value -3 to Vboot - 18 - 0.3 to +18 - 1 to 618 - 1 to Vboot -0.3 to Vcc +0.3 -0.3 to Vcc +0.3 50 750 150 -50 to 150 Unit V V V V V V V/ns mW C C Note: ESD immunity for pins 6, 7 and 8 is guaranteed up to 900V (Human Body Model) Figure 3. Pin Connection (Top view) LIN HIN VCC GND 1 2 3 4 D97IN517A 8 7 6 5 Vboot HVG OUT LVG Table 3. Pin Description N. 1 2 3 4 5 6 7 8 Name LIN HIN Vcc GND LVG (*) OUT HVG (*) Vboot O O O Type I I I Low Side Driver Logic Input High Side Driver Logic Input Low Voltage Power Supply Ground Low Side Driver Output High Side Driver Floating Reference High Side Driver Output Bootstrap Supply Voltage Function (*) The circuit guarantees 0.3V maximum on the pin (@ Isink = 10mA). This allows to omit the "bleeder" resistor connected between the gate and the source of the external MOSFET normally used to hold the pin low. Table 4. Thermal Data Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient SO8 150 Minidip 100 Unit C/W 2/11 L6388 Table 5. Recommended Operating Conditions Symbol Vout VBS (*) fsw Vcc Tj 3 Pin 6 8 Parameter Output Voltage Floating Supply Voltage Switching Frequency Supply Voltage Junction Temperature -45 HVG,LVG load CL = 1nF Test Condition Min. Note 1 Note 1 Typ. Max. 580 17 400 17 125 Unit V V kHz V C Note 1: If the condition Vboot - Vout < 18V is guaranteed, Vout can range from -3 to 580V (*): VBS = Vboot - Vout Table 6. Electrical Characteristics (Vcc = 15V; Tj = 25C) Symbol Pin Parameter Test Condition Min. Typ. Max. Unit AC OPERATION ton toff tr tf DT 7,5 7,5 7,5 1 vs 5 High/Low Side Driver Turn-On 2 vs 7 Propagation Delay High/Low Side Driver Turn-Off Propagation Delay Rise Time Fall Time Dead Time Vout = 0V Vout = 0V CL = 1000pF CL = 1000pF 220 225 160 70 40 320 300 220 100 80 420 ns ns ns ns ns DC OPERATION Low Supply Voltage Section Vccth1 Vccth2 Vcchys Iqccu Iqcc Rdson 3 Vcc UV Turn On Threshold Vcc UV Turn Off Threshold Vcc UV Hysteresis Undervoltage Quiescent Supply Current Quiescent Current Vcc 9V Vcc = 15V 9.1 7.9 0.9 250 350 125 330 450 9.6 8.3 10.1 8.8 V V V A A Bootstrap Driver on Resistance (**) Vcc Bootstrapped Supply Voltage Section VBSth1 VBSth2 VBShys IQBS ILK 8 VBS UV Turn On Threshold VBS UV Turn Off Threshold VBS UV Hysteresis VBS Quiescent Current High Voltage Leakage Current HVG ON Vhvg = Vout = Vboot = 600V 8.5 7.2 0.9 250 10 9.5 8.2 10.5 9.2 V V V A A High/Low Side Driver Iso Isi 5,7 Source Short Circuit Current Sink Short Circuit Current VIN = Vih (tp < 10s) VIN = Vil (tp < 10s) 300 500 400 650 mA mA 3/11 L6388 Table 6. Electrical Characteristics (continued) (Vcc = 15V; Tj = 25C) Symbol Pin Parameter Test Condition Min. Typ. Max. Unit Logic Inputs Vil Vih Iih Iil 1, 2 Low Level Logic Input Voltage High Level Logic Input Voltage High Level Logic Input Current Low Level Logic Input Current VIN = 15V VIN = 0V -1 1.8 20 70 1.1 V V A A (**) RDSON is tested in the following way: R DSON = ------------------------------------------------------------------------------------------------------------I 1 ( V CC, V CCBOOT1 ) - I 2 ( V CC, V CCBOOT2 ) where I1 is pin 8 current when VCBOOT = VCBOOT1, I2 when VCBOOT = VCBOOT2. ( V CC - V CBOOT1 ) - ( V CC - V CBOOT2 ) Figure 4. Dead Time Waveforms Definitions LIN H IN DT DT LVG DT HVG Figure 5. Propagation Delay Waveform Definitions LIN 50% 50% 50% > DT > DT 50% 50% HIN ton Interlocking function 90% 10% toff LVG ton 90% HVG 10% toff 4/11 L6388 3 INPUT LOGIC Input logic is provided with an interlocking circuitry which avoids the two outputs (LVG, HVG) to be active at the same time when both the logic input pins (LIN, HIN) are at a high logic level. In addition, to prevent cross conduction of the external MOSFETs, after each output is turned-off the other output cannot be turned-on before a certain amount of time (DT) (see Figure 4). Figure 6. Typical Rise and Fall Times vs. Load Capacitance time (nsec) 250 200 Tr 150 Tf 100 50 0 D99IN1054 Figure 7. Quiescent Current vs. Supply Voltage Iq (A) 104 D99IN1055 103 102 10 0 1 2 3 4 5 C (nF) For both high and low side buffers @25C Tamb 0 2 4 6 8 10 12 14 16 VS(V) 3.1 BOOTSTRAP DRIVER A bootstrap circuitry is needed to supply the high voltage section. This function is normally accomplished by a high voltage fast recovery diode (fig. 8a). In the L6388 a patented integrated structure replaces the external diode. It is realized by a high voltage DMOS, driven synchronously with the low side driver (LVG), with in series a diode, as shown in fig. 8b An internal charge pump (fig. 8b) provides the DMOS driving voltage . The diode connected in series to the DMOS has been added to avoid undesirable turn on of it. 3.2 CBOOT selection and charging To choose the proper CBOOT value the external MOS can be seen as an equivalent capacitor. This capacitor CEXT is related to the MOS total gate charge : Q gate C EXT = -------------V gate The ratio between the capacitors CEXT and CBOOT is proportional to the cyclical voltage loss . It has to be: CBOOT>>>CEXT e.g.: if Qgate is 30nC and Vgate is 10V, CEXT is 3nF. With CBOOT = 100nF the drop would be 300mV. If HVG has to be supplied for a long time, the CBOOT selection has to take into account also the leakage losses. e.g.: HVG steady state consumption is lower than 200A, so if HVG TON is 5ms, CBOOT has to supply 1C to CEXT. This charge on a 1F capacitor means a voltage drop of 1V. The internal bootstrap driver gives great advantages: the external fast recovery diode can be avoided (it usually has great leakage current). This structure can work only if VOUT is close to GND (or lower) and in the meanwhile the LVG is on. The charging time (Tcharge) of the CBOOT is the time in which both conditions are fulfilled and it 5/11 L6388 has to be long enough to charge the capacitor. The bootstrap driver introduces a voltage drop due to the DMOS RDSON (typical value: 125 Ohm). At low frequency this drop can be neglected. Anyway increasing the frequency it must be taken in to account. The following equation is useful to compute the drop on the bootstrap DMOS: Q gate V drop = I ch arg e R dson V drop = ------------------- R dson T ch arg e where Qgate is the gate charge of the external power MOS, Rdson is the on resistance of the bootstrap DMOS, and Tcharge is the charging time of the bootstrap capacitor. For example: using a power MOS with a total gate charge of 30nC the drop on the bootstrap DMOS is about 1V, if the Tcharge is 5s. In fact: 30nC V drop = -------------- 125 0.8V 5s Vdrop has to be taken into account when the voltage drop on CBOOT is calculated: if this drop is too high, or the circuit topology doesn't allow a sufficient charging time, an external diode can be used. Figure 8. Bootstrap Driver. DBOOT VS VBOOT H.V. HVG CBOOT VOUT TO LOAD LVG a VBOOT H.V. HVG VS CBOOT VOUT TO LOAD LVG b 6/11 L6388 Figure 9. VBOOT UV Turn On Threshold vs. Temperature 13 12 11 Vccth2(V) VBSth1(V) Typ. Figure 12. VCC UV Turn Off Threshold vs. Temperature 11 @ Vcc = 15V 10 9 Typ. 10 9 8 7 6 5 8 7 6 -45 -25 0 25 50 Tj (C) 75 100 125 -45 -25 0 25 50 75 100 125 Tj (C) Figure 10. VBOOT UV Turn Off Threshold vs. Temperature 14 13 12 11 Figure 13. Output Source Current vs. Temperature 1000 @ Vcc = 15V current (mA) @ Vcc = 15V 800 600 Typ. VBSth2(V) 10 9 8 7 6 -45 -25 0 25 50 75 100 125 Typ. 400 200 0 -45 -25 0 25 50 Tj (C) 75 100 125 Figure 11. VCC UV Turn On Threshold vs. Temperature 13 12 Figure 14. Output Sink Current vs. Temperature 1000 @ Vcc = 15V 800 current (mA) 600 400 200 0 Vccth1(V) 11 10 9 8 7 -45 -25 0 25 50 Tj (C) 75 100 125 Typ. Typ. -45 -25 0 25 50 Tj (C) 75 100 125 7/11 L6388 Figure 15. DIP8 Mechanical Data & Package Dimensions mm DIM. MIN. A a1 B b b1 D E e e3 e4 F I L Z 3.18 7.95 2.54 7.62 7.62 6.6 5.08 3.81 1.52 0.125 0.51 1.15 0.356 0.204 1.65 0.55 0.304 10.92 9.75 0.313 0.100 0.300 0.300 0.260 0.200 0.150 0.060 TYP. 3.32 0.020 0.045 0.014 0.008 0.065 0.022 0.012 0.430 0.384 MAX. MIN. TYP. 0.131 MAX. inch OUTLINE AND MECHANICAL DATA DIP-8 8/11 L6388 Figure 16. SO8 Mechanical Data & Package Dimensions mm DIM. MIN. A A1 A2 B C D (1) E e H h L k ddd 5.80 0.25 0.40 1.35 0.10 1.10 0.33 0.19 4.80 3.80 1.27 6.20 0.50 1.27 0.228 0.010 0.016 TYP. MAX. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 MIN. 0.053 0.004 0.043 0.013 0.007 0.189 0.15 0.050 0.244 0.020 0.050 TYP. MAX. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 inch OUTLINE AND MECHANICAL DATA 0 (min.), 8 (max.) 0.10 0.004 Note: (1) Dimensions D does not include mold flash, protrusions or gate burrs. Mold flash, potrusions or gate burrs shall not exceed 0.15mm (.006inch) in total (both side). SO-8 0016023 C 9/11 L6388 Table 7. Revision History Date January 2005 May 2005 Revision 1 2 First Issue Changed from Preliminary Data to Final Description of Changes 10/11 L6388 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 11/11 |
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